MSME
Date
30 May 2020
Webinar on VLSI Front End
Resource Person : Priya Anathakrishnan Corporate Technical Trainer
Date : 30th May 2020
Time : 02.00 PM – 03.00 PM
Via : Zoom Meetings / YouTube
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Activity Name |
VLSI Front End on 30-May-2020 |
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Activity Type |
Lecture |
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Conducted By |
CTDS Bangalore |
About the Activity
VLSI Front End on 30-May-2020
Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for describing a digital system like a network switch or a microprocessor or a memory or a flip−flop. It means, by using an HDL we can describe any digital hardware at any level. Designs, which are described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
Presented by Mrs. Priya Ananthakrishnan, Corporate Technical Trainer & Former Senior VLSI Trainer, ChipEdge Technologies Pvt Ltd, Bangalore.
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